Quad-Layer 3D Stacking Technology Enables Chips of the Future

True next-gen 3D chip stacking may be right around the corner, as researches from the Institute of Microeletronics (IME) have just achieved a technology breakthrough that enables up to four semiconductor layers to be stacked. This enables up to 50% savings compared to traditional 2D fabrication techniques, and the technique will likely be used in the best CPUs and best graphics cards of the future.

This achievement is a step-up from the AMD-announced, TSMC-enabled SRAM stacking that’s bound to grace our computers by the end of this year, as that particular process currently only enables two dies (in AMD’s case, a Zen 3 CCX on layer one and 96MB of SRAM cache on layer two) to be bonded together. The IME researchers have shown a process where they successfully bonded four separate silicon layers via TSVs (Through-Silicon-Vias), the information highways allowing communication between the different dies. 

Lisa Su holding a 3D-stacked Ryzen 9 CPU

AMD’s Lisa Su holds a Ryzen 9 CPU with vertically-stacked SRAM. (Image credit: AMD)

TSVs and the active wafer stacking they enable are hailed as one of the most important technological breakthroughs for sustaining (and perhaps even improving upon) Moore’s Law, since they allow for wider information buses that need not operate at extremely high frequencies to achieve performance goals. This, in turn, enables denser designs, since some components that were previously arranged horizontally can now be vertically stacked. It also allows for higher power efficiency, more efficient heat dissipation, and even offers improvements do yields. That last is because different components that go into a CPU, for instance, can now be manufactured in different wafers instead of the old, monolithic approach, automatically increasing resilience to manufacturing defects.

Bonding a four-layer 3D silicon stack

The (extremely simplified) three-step process of bonding and actively connecting a four-layer 3D silicon stack. (Image credit: IME)

The manufacturing approach implemented by IME was achieved “…by combining Face-to-Face and Back-to-Back wafer bonding with onestep TSV after stacking.” This means that the first, base layer has its “face” towards the second layer, which is also facing it; and the second layer has its “back” towards the third layer’s back, which in turn faces the fourth layer’s face. After these layers were bonded, IME then proceeded to “punch” them by etching along specifically-designed pathways that finally become the TSVs through which data flows.


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